MC68HC08XL36 Datasheet, PDF (306/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
IRQ
IRQ Module During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear CPU interrupt requests during the break state. (See Break
Module (BRK) on page 141.)
To allow software to clear IRQ1 and IRQ2 CPU interrupt requests during
a break interrupt, write a logic 1 to the BCFE bit. If a CPU interrupt
request is cleared during the break state, it remains cleared when the
MCU exits the break state.
To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK1
and ACK2 bits in the IRQ status and control register during the break
state has no effect on the IRQ interrupt flags.
IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. The ISCR has the following functions:
• Shows the state of the IRQ1 and IRQ2 interrupt flags
• Clears IRQ1 and IRQ2 CPU interrupt flags
• Masks IRQ1 and IRQ2 CPU interrupt requests
• Controls triggering sensitivity of the IRQ1 and IRQ2 CPU interrupt
pins
MC68HC08XL36
306
External Interrupt Module (IRQ)
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8-intirq2_a
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