MC68HC08XL36 Datasheet, PDF (353/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Index
Index
A
accumulator (A) . . . . . . . . . . . . . . . . . . . . .41
ACK1 bit (IRQ1 pin interrupt request acknowl-
edge bit) . . . . . . . . . . . . . . . . . . . . .308
during break interrupts . . . . . . . . . . . .306
polling the IRQ1 pin . . . . . . . . . . . . . .303
ACK2 bit (IRQ2 pin interrupt request acknowl-
edge bit) . . . . . . . . . . . . . . . . . . . . .307
during break interrupts . . . . . . . . . . . .306
polling the IRQ2 pin . . . . . . . . . . . . . .304
ACKK bit (keyboard acknowledge bit) . . .316
ACQ bit (acquisition mode bit) . . . . . . . . . .97
ADC instruction . . . . . . . . . . . . . . . . . . . . .44
ADD instruction . . . . . . . . . . . . . . . . . . . . .44
arithmetic/logic unit (ALU) . . . . . . . . . . . . .46
AUTO bit (automatic bandwidth control bit) 97
B
BB0 and BB1 bits (DMA bus bandwidth control
bits) . . . . . . . . . . . . . . . . . . . . . . . .129
BCD arithmetic . . . . . . . . . . . . . . . . . . . . . .44
BCFE bit (break clear flag enable bit) . . .148
DMA status bits . . . . . . . . . . . . . . . . . .127
IRQ interrupt requests . . . . . . . . . . . . .306
KBI interrupt requests . . . . . . . . . . . . .314
SCI status bits . . . . . . . . . . . . . . . . . . .251
BCS bit (base clock select bit) . . . . . . . . . .96
BIH instruction . . . . . . . . . . . . . . . . . . . . .303
BIL instruction . . . . . . . . . . . . . . . . . . . . . .303
BKF bit (SCI break flag bit) . . . . . . . . . . . .266
break address registers (BRKH/L) . . . . . .147
break character . . . . . . . . . . . . . . . . . . . .236
in monitor data . . . . . . . . . . . . . . . . . .154
break flag control register (BFCR) . . . . . .148
break interrupt
causes . . . . . . . . . . . . . . . . . . . . . . . . .142
effects on COP . . . . . . . . . . . . . . . . . .144
effects on CPU . . . . . . . . . . . . . . . . . .144
effects on DMA . . . . . . . . . . . . . . . . . .144
effects on TIM . . . . . . . . . . . . . . . . . . .144
break status and control register (BSCR) 146
break status register (BSR) . . . . . . . . . . .147
BRKA bit (break active bit) . . . . . . . . . . . .146
BRKE bit (break enable bit) . . . . . . . . . . .146
bus frequency . . . . . . . . . . . . . . . . . . . . . . .12
BW bit (break/wait bit) . . . . . . . . . . . . . . .148
BWC bit (DMA byte/word control bit) . . . .136
C
C bit (carry/borrow flag) . . . . . . . . . . . . . . .45
CGMOUT signal . . . . . . . . . . . . . . . . . . . . .94
CGMVCLK signal . . . . . . . . . . . . . . . . . . . .82
CGMXCLK signal . . . . . . . . . . . . . . . . . . . .93
CGMXFC pin . . . . . . . . . . . . . . . . . . . . . . .18
CGND pin . . . . . . . . . . . . . . . . . . . . . . . . .218
CGND/EV_SS pin . . . . . . . . . . . . . . . . . . . . .18
CHxF bits (TIM channel interrupt flag bits) . . .
185
CHxIE bits (TIM channel interrupt enable bits)
. . . . . . . . . . . . . . . . . . . . . . . . . . . .186
CHxMAX bits (TIM maximum duty cycle bits)
189
CLI instruction . . . . . . . . . . . . . . . . . . . . . .45
condition code register (CCR) . . . . . . . . . .44
COP bit (COP reset bit) . . . . . . . . . . . . . . .59
COP control register (COPCTL) . . . . . . . .296
COP counter . . . . . . . . . . . . . . . . . . . . . .294
COP timeout period . . . . . . . . . . . . . . . . .294
CPHA bit (SPI clock phase bit) . . . . . . . .220
CPOL bit (SPI clock polarity bit) . . . . . . . .220
CPU interrupt requests
DMA block transfer complete . . . . . . .131
MOTOROLA
Index
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MC68HC08XL36
353