MC68HC08XL36 Datasheet, PDF (144/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
BRK
Flag Protection
During Break
Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
CPU During Break
Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction.
• Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode).
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
DMA During Break
Interrupts
If the DMA is enabled, clear the DMAP bit in the DMA status and control
register before executing a break interrupt.
If a break interrupt is asserted during the current address cycle and the
DMA is active, the DMA releases the internal address and data buses at
the next address boundary to preserve the current MCU state. During
the break interrupt, the DMA continues to arbitrate DMA channel
priorities. After the break interrupt, the DMA becomes active again and
resumes transferring data according to its highest priority service
request.
TIM During Break
Interrupts
A break interrupt stops the timer counter.
COP During Break The COP is disabled during a break interrupt when V_DD + V_Hi is present
Interrupts
on the RST pin.
MC68HC08XL36
144
Break Module (BRK)
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4-brk_a
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