MC68HC08XL36 Datasheet, PDF (130/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
Freescale Semiconductor, Inc.
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 15. Multiple Byte/Word Transfer Timing: 25% DMA Bus Bandwidth
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 16. Multiple Byte/Word Transfer Timing: 50% DMA Bus Bandwidth
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 17. Multiple Byte/Word Transfer Timing: 67% DMA Bus Bandwidth
NOTE:
When two or more DMA channels have transfers pending, the CPU
executes at least one cycle between each DMA block length, even if the
DMA channels have 100% of the bus bandwidth.
MC68HC08XL36
130
Direct Memory Access Module (DMA)
For More Information On This Product,
Go to: www.freescale.com
24-dma_b
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