MC68HC08XL36 Datasheet, PDF (136/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
Freescale Semiconductor, Inc.
Table 9. Source/Destination Address Register Control
SDC[3:2:1:0]
1010
1001
1000
0110
0101
0100
0010
0001
0000
Source Address
Increment
Increment
Increment
Decrement
Decrement
Decrement
Static
Static
Static
Destination Address
Increment
Decrement
Static
Increment
Decrement
Static
Increment
Decrement
Static
The DMA calculates an incremented address by adding the byte
count register to the base address. To calculate a decremented
address, the DMA subtracts the byte count register from the base
address. To determine a static address, the DMA reads the base
address.
BWC — Byte/Word Control Bit
This read/write bit determines whether the DMA channel transfers
8-bit bytes or 16-bit words. The BWC bit has no effect unless either
the source or destination address is static or both are static.
1 = 16-bit words
0 = 8-bit bytes
NOTE:
To transfer a block of 16-bit words (BWC = 1), set the block length to the
number of words times two. (See DMA Block Length Registers on page
139.)
When both the source and destination addresses are static, the first byte
of the word transfers from the source base address to the destination
base address. The second byte transfers from the source base address
plus one to the destination address plus one. When either the source or
destination address increments or decrements, the DMA transfers bytes
from or to incrementing or decrementing addresses.
MC68HC08XL36
136
Direct Memory Access Module (DMA)
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