MC68HC08XL36 Datasheet, PDF (305/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
Low-Power Modes
There is no direct way to determine the logic level on the IRQ2 pin.
However, it is possible to use the IRQF2 bit in the ISCR to infer the state
of the IRQ2 pin. If the MODE2 bit is a logic 1, the IRQF2 bit in the ISCR
is the opposite value of the IRQ2 pin as long as the IRQ2 CPU interrupt
request is cleared. (See Figure 1.) Clear the IRQ2 CPU interrupt request
by writing a logic 1 to the acknowledge bit. Recall, however, that every
falling edge on the IRQ2 pin latches an IRQ2 CPU interrupt request. So
an additional acknowledge is necessary after each falling edge on IRQ2
to maintain the opposite relationship between IRQF2 and the IRQ2 pin.
Set the IMASK2 bit in the ISCR to prevent the IRQF2 from generating
CPU interrupts when used in this manner.
NOTE:
To avoid spurious CPU interrupts caused by noise, mask CPU interrupt
requests in the interrupt routine when using the level-sensitive interrupt
trigger.
Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-consump-
tion standby modes.
Wait Mode
The IRQ module remains active in wait mode. Clearing the IMASK1 or
IMASK2 bit in the IRQ status and control register enables IRQ1 or IRQ2
CPU interrupt requests to bring the MCU out of wait mode.
Stop Mode
The IRQ module remains active in stop mode. Clearing the IMASK1 or
IMASK2 bit in the IRQ status and control register enables IRQ1 or IRQ2
CPU interrupt requests to bring the MCU out of stop mode.
7-intirq2_a
MOTOROLA
External Interrupt Module (IRQ)
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MC68HC08XL36
305