MC68HC08XL36 Datasheet, PDF (307/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
IRQ Status and Control Register
Address: $0032
Bit 7
6
5
4
3
2
1
Bit 0
Read: IRQF2
Write:
0
ACK2
IMASK2 MODE2
IRQF1
0
ACK1
IMASK1 MODE1
Reset:
= Unimplemented
Figure 2. IRQ Status and Control Register (ISCR)
IRQ2F — IRQ2 Flag
This read-only bit is high when an IRQ2 CPU interrupt is pending.
Reset clears IRQ2F.
1 = IRQ2 CPU interrupt pending
0 = IRQ2 CPU interrupt not pending
ACK2 — IRQ2 Interrupt Request Acknowledge Bit
Writing a logic 1 to this write-only bit clears the IRQ2 CPU interrupt
request. ACK2 always reads as logic 0. Reset clears ACK2.
IMASK2 — IRQ2 Interrupt Mask Bit
Writing a logic 1 to this read/write bit disables IRQ2 CPU interrupt
requests. Reset clears IMASK2.
1 = IRQ2 CPU interrupt requests masked
0 = IRQ2 CPU interrupt requests not masked
MODE2 — IRQ2 Pin Edge/Level Select Bit
This read/write bit controls the triggering sensitivity of the IRQ2 pin.
Reset clears MODE2.
1 = IRQ2 CPU interrupt requests on falling edges and low levels
0 = IRQ2 CPU interrupt requests on falling edges only
IRQ1F — IRQ1 Flag
This read-only bit is high when an IRQ1 CPU interrupt is pending.
1 = IRQ1 CPU interrupt pending
0 = IRQ1 CPU interrupt not pending
9-intirq2_a
MOTOROLA
External Interrupt Module (IRQ)
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MC68HC08XL36
307