MC68HC08XL36 Datasheet, PDF (129/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA Control
Register 1
Freescale Semiconductor, Inc.
Direct Memory Access Module (DMA)
DMA Registers
DMA control register 1:
• Enables channels to transfer data when DMA service requests
occur.
• Enables channels to generate CPU interrupt requests.
• Controls how much of the bus bandwidth the DMA uses.
Address: $004C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BB1
Write:
BB0 TEC2 IEC2 TEC1 IEC1 TEC0 IEC0
Reset: 0
0
0
0
0
0
0
0
Figure 14. DMA Control Register 1 (DC1)
BB1 and BB0 — Bus Bandwidth Control Bits
These read/write bits control the ratio of DMA/CPU bus activity during
a DMA transfer. As Table 6 shows, the DMA can use 25%, 50%, 67%,
or 100% of the bus bandwidth. Reset clears bits BB1 and BB0.
Table 6. DMA/CPU Bus Control Selection
BB1:BB0
00
01
10
11
DMA Transfer
DMA Bus Cycles
CPU Bus Cycles
2 (25%)
6 (75%)
2 (50%)
2 (50%)
2 (67%)
1 (33%)
All (100%)
0 (0%)
Figure 15, Figure 16, and Figure 17 show the timing of DMA
transfers with DMA bus bandwidths of 25%, 50%, and 67%.
23-dma_b
MOTOROLA
Direct Memory Access Module (DMA)
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MC68HC08XL36
129