MC68HC08XL36 Datasheet, PDF (131/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Direct Memory Access Module (DMA)
DMA Registers
For DMA transfers of one byte or one word, giving the DMA 100% of
the bus bandwidth is appropriate. However, for large,
software-initiated transfers, limiting the bus bandwidth of the DMA
may be useful to keep from slowing CPU activity.
TEC2–TEC0 — Transfer Enable Bits
These read/write bits enable the corresponding channels to perform
transfers when DMA service requests occur. When two or more
channels are enabled, a transfer on one channel cannot begin while
another channel is transferring a byte or word. Reset clears the
TEC2–TEC0 bits.
1 = Corresponding DMA channel enabled
0 = Corresponding DMA channel disabled
IEC2–IEC0 — CPU Interrupt Enable Bits
These read/write bits enable the corresponding channels to generate
CPU interrupt requests upon completion of DMA block transfers or at
the restart of DMA transfer loops. Reset clears the IEC2–IEC0 bits.
1 = CPU interrupts from corresponding channel enabled
0 = CPU interrupts from corresponding channel disabled
DMA Status and
Control Register
The DMA status and control register:
• Flags completion of DMA transfers.
• Controls looping of source and destination address counts.
• Controls priority of DMA service requests and CPU interrupt
requests.
Address: $004D
Bit 7
6
5
4
3
2
1
Bit 0
Read:
DMAP
L2
L1
L0 DMAWE IFC2 IFC1 IFC0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 18. DMA Status and Control Register (DSC)
25-dma_b
MOTOROLA
Direct Memory Access Module (DMA)
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MC68HC08XL36
131