MC68HC08XL36 Datasheet, PDF (209/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Error Conditions
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the
SPRF, MODF, and OVRF interrupts share the same CPU interrupt
vector. When the DMAS bit is high, SPRF generates a receiver DMA
service request instead of a CPU interrupt request, but MODF and
OVRF can generate a receiver/error CPU interrupt request. (See Figure
12 on page 212.) It is not possible to enable MODF or OVRF individually
to generate a receiver/error CPU interrupt request. However, leaving
MODFEN low prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of
port drivers.
NOTE:
When the MODF flag is set, it does not clear the SPMSTR bit. The
SPMSTR bit has no function when SPE = 0. Reading SPMSTR when
MODF = 1 indicates whether the SPI was a master or a slave when
MODF became set.
NOTE:
To prevent bus contention with another master SPI after a mode fault
error, clear all SPI bits of the data direction register of the shared I/O port
before enabling the SPI.
19-spi_c
MOTOROLA
Serial Peripheral Interface Module (SPI)
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MC68HC08XL36
209