MC68HC08XL36 Datasheet, PDF (355/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Index
IDLE bit (SCI receiver idle bit) . . . . . . . . .264
idle character . . . . . . . . . . . . . . . . . . . . . .236
IECx bits (DMA CPU interrupt enable bits) . .
131
IFCx bits (DMA CPU interrupt flag bits) . .134
ILAD bit (illegal address reset bit) . . . . . . .59
ILIE bit (SCI idle line interrupt enable bit) .257
ILOP bit (illegal opcode reset bit) . . . . . . . .59
ILTY bit (SCI idle line type bit) . . . . . . . . .254
IMASK1 bit (IRQ1 pin interrupt mask bit) .308
IMASK2 bit (IRQ2 pin interrupt mask bit) .307
IMASKK (keyboard interrupt mask bit) . . .316
index register (H:X) . . . . . . . . . . . . . . . . . .42
input capture . . . . . . . . . . . . . . . . . . . . . . .168
internal reset sources . . . . . . . . . . . . . . . . .56
IRQ status and control register (ISCR) . . .306
IRQ1 pin . . . . . . . . . . . . . . . . . . . . . . . . . .302
reading the pin level . . . . . . . . . . . . . .303
triggering sensitivity . . . . . . . . . . . . . .302
IRQ2 pin . . . . . . . . . . . . . . . . . . . . . . . . . .304
determining the pin level . . . . . . . . . . .305
triggering sensitivity . . . . . . . . . . . . . .302
IRQ2F bit (IRQ2 pin interrupt flag) . . . . . .307
K
KBIEx bits (keyboard interrupt enable bits) . .
316
data direction override . . . . . . . . . . . .312
keyboard interrupt enable register (KBIER) . .
316
keyboard interrupt pins . . . . . . . . . . . . . . . .19
keyboard status and control register (KBSCR)
. . . . . . . . . . . . . . . . . . . . . . . . . . . .315
KEYF bit (keyboard pin interrupt flag bit) .315
L
L (VCO linear range multiplier) . . . . . . . . . .90
L2–L0 bits (DMA loop enable bits) . . . . . .133
literature distribution centers . . . . . . . . . .359
LOCK bit (lock indicator bit) . . . . . . . . . . . .97
LOOPS bit (SCI loop mode select bit) . . .253
LVI bit (low-voltage inhibit reset bit) . . . . . .58
LVI bit (LVI reset bit) . . . . . . . . . . . . . . . . . .59
LVI status register (LVISR) . . . . . . . . . . .319
LVIOUT bit (LVI output bit) . . . . . . . . . . . .319
M
M bit (SCI character length bit) . . . . . . . .254
M6805 compatibility . . . . . . . . . . . . . . . . . .36
MODE1 bit (IRQ1 pin edge/level select bit) . .
308
MODE2 bit (IRQ2 pin edge/level select bit) . .
307
MODEK bit (keyboard pin edge/level select
bit) . . . . . . . . . . . . . . . . . . . . . . . . .316
MODF bit (SPI mode fault bit) . . . . . . . . .223
monitor mode baud rate . . . . . . . . . . . . . .154
MSxA/B bits (TIM mode select bits) . . . . .186
N
N (VCO frequency multiplier) . . . . . . . . . . .89
N bit (negative flag) . . . . . . . . . . . . . . . . . .45
NEIE bit (SCI receiver noise error interrupt en-
able bit) . . . . . . . . . . . . . . . . . . . . .261
NF bit (SCI noise flag bit) . . . . . . . . . . . . .265
noise
power supply bypassing . . . . . . . . . . . .17
O
object code compatibility . . . . . . . . . . . . . .12
OR bit (SCI receiver overrun bit) . . . . . . .264
ordering information
literature distribution centers . . . . . . . .359
Mfax . . . . . . . . . . . . . . . . . . . . . . . . . .360
Web server . . . . . . . . . . . . . . . . . . . . .360
Web site . . . . . . . . . . . . . . . . . . . . . . .360
ORIE bit (SCI receiver overrun interrupt en-
able bit) . . . . . . . . . . . . . . . . . . . . .261
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . . . . .17
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . .17
oscillator
pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
oscillator stabilization delay . . . . . . . . . . . .57
output compare . . . . . . . . . . . . . . . . . . . .169
OVRF bit (SPI overflow bit) . . . . . . . . . . .223
MOTOROLA
Index
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MC68HC08XL36
355