MC68HC08XL36 Datasheet, PDF (64/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
SWI Instruction
The software interrupt instruction (SWI) causes a nonmaskable
interrupt.
NOTE: A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
Break Interrupt
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
IRQ1 Pin
A logic 0 on the IRQ1 pin latches an external interrupt request.
CGM
The CGM can generate a CPU interrupt request every time the
phase-locked loop circuit (PLL) enters or leaves the locked state. When
the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
DMA
The DMA module can generate a CPU interrupt request when a channel
x CPU interrupt flag (IFCx) becomes set.
• IFCx is set at the end of a DMA block transfer. The channel x CPU
interrupt enable bit, IECx, enables DMA channel x CPU interrupt
requests.
• IFCx is set at the end of a DMA transfer loop. The channel x CPU
interrupt enable bit, IECx, enables DMA channel x CPU interrupt
requests.
The IFCx bit is the DMA status and control register. The IECx bit is in
DMA control register 1.
TIM
TIM CPU interrupt sources:
• TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
MC68HC08XL36
64
Resets and Interrupts
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