ATMEGA8U2_14 Datasheet, PDF (90/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• Bits 6:1 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters
When this bit is one, Timer/Counter0 and Timer/Counter1, Timer/Counter3, Timer/Counter4 and
Timer/Counter5 prescaler will be Reset. This bit is normally cleared immediately by hardware,
except if the TSM bit is set. Note that Timer/Counter0 and Timer/Counter1 share the same pres-
caler and a reset of this prescaler will affect all timers.
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