ATMEGA8U2_14 Datasheet, PDF (150/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 18-2 shows a block diagram of the clock generation logic.
Figure 18-2. Clock Generation Logic, Block Diagram
UBRR
fosc
Prescaling
Down-Counter
UBRR+1
/2
/4
OSC
XCK
Pin
xcki
xcko
Sync
Register
Edge
Detector
U2X
/2
0
1
DDR_XCK
0
txclk
1
0
UMSEL
1
DDR_XCK
UCPOL
1
rxclk
0
18.3.1
Signal description:
txclk
rxclk
xcki
xcko
f_OSC
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave operation.
Clock output to XCK pin (Internal Signal). Used for synchronous master operation.
XTAL pin frequency (System Clock).
Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to Figure 18-2.
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f_osc), is loaded with the UBRRn value each time the counter has counted down to zero or when
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f_osc/(UBRRn+1)). The Transmitter divides the
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
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