ATMEGA8U2_14 Datasheet, PDF (190/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
20.4.3 Interrupts
When the USB controller is in reset state:
• USBE is not set
• the USB controller clock is stopped in order to minimize the power consumption (FRZCLK=1)
• the USB controller is disabled
• USB is in the suspend mode
• the Device USB controllers internal state is reset
• The DPACC bit and the DPADD10:0 field can be set by software. The DPRAM is not cleared.
• The SPDCONF bits can be set by software
After setting USBE, the USB Controller enters in the Device state.
The USB Controller can at any time be reset by clearing USBE.
Two interrupts vectors are assigned to the USB controller.
Figure 20-8. USB Interrupt System
USB Device
Interrupt
Endpoint
Interrupt
USB General
Interrupt Vector
USB Endpoint/Pipe
Interrupt Vector
The USB module distinguishes between USB General events and USB Endpoints events.
Figure 20-9. USB General interrupt vector sources
UPRSMI
UDINT.6
EORSMI
UDINT.5
WAKEUPI
UDINT.4
EORSTI
UDINT.3
SOFI
UDINT.2
SUSPI
UDINT.0
UPRSME
UDIEN.6
EORSME
UDIEN.5
WAKEUPE
UDIEN.4
EORSTE
UDIEN.3
SOFE
UDIEN.2
SUSPE
UDIEN.0
USB General
Interrupt Vector
Asynchronous Interrupt source
(allows the CPU to wake up from power down mode)
The WAKEUP interrupt allows device wake-up from power-down mode, and is an asynchronous
interrupt, triggering each time a state change is detected on the data lines. The other interrupts
are synchronous and will be detected only if the USB clock is enabled (FRZCLK bit set).
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