ATMEGA8U2_14 Datasheet, PDF (216/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
21.18.12 UECFG1X – USB Endpoint Configuration 1 Register
Bit
7
(0xED)
-
Read/Write
R
Initial Value
0
6
5
4
EPSIZE[2:0]
R/W
R/W
R/W
0
0
0
3
2
EPBK1:0
R/W
R/W
0
0
1
ALLOC
R/W
0
0
-
UECFG1X
R
0
• Bit 7 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 6:4 – EPSIZE[2:0]: Endpoint Size Bits
These bits configure the endpoint size for the selected endpoint as shown in Table 21-3.
Table 21-3. EPSIZE[2:0] Bits Settings
EPSIZE2
EPSIZE1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
EPSIZE0
0
1
0
1
0
1
0
1
Endpoint Size
8 Bytes
16 Bytes
32 Bytes
64 Bytes
Reserved.
• Bits 3:2 – EPBK[1:0]: Endpoint Bank Bits
These bits configure the number of banks that is allocated to the selected endpoint as shown in
Table 21-3.
Table 21-4. EPBK[1:0] Bits Settings
EPBK1
EPBK0
0
0
0
1
1
0
1
1
Endpoint Size
One Bank
Two Banks
Reserved
• Bit 1 – ALLOC: Endpoint Allocation Bit
Writing this to one allows to allocate the specified amount of memory (endpoint size x number of
banks) for the selected endpoint. Writing this bit to zero allows to free the previously allocated
memory for the selected endpoint.
See Section 21.6, page 198 for more details.
• Bit 0 – Res: Reserved
This bit is reserved and will always read as zero.
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