ATMEGA8U2_14 Datasheet, PDF (48/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Figure 10-1. Reset Logic
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
Brown-out
Reset Circuit
USB Device
Reset Detection
Watchdog
Oscillator
Clock
CK
Generator
Delay Counters
TIMEOUT
CKSEL[3:0]
SUT[1:0]
10.2.1
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 267. The POR is activated whenever
V_CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V_CC rise. The RESET signal is activated again, without any delay,
when V_CC decreases below the detection level.
Figure 10-2. MCU Start-up, RESET Tied to V_CC
V_CC
V_POT
RESET
V_RST
TIME-OUT
t_TOUT
INTERNAL
RESET
48
7799D–AVR–11/10