ATMEGA8U2_14 Datasheet, PDF (177/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 19-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud Rate⁽¹⁾
Equation for Calculating UBRRn Value
Synchronous Master mode
BAUD = --------------^f---^O----^S---^C--------------
2UBRRn + 1
UBRRn = -----^f---^O----^S---^C----- – 1
2BAUD
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
Baud rate (in bits per second, bps)
f_OSC
UBRRn
System Oscillator clock frequency
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
19.4
SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are
shown in Figure 19-1. Data bits are shifted out and latched in on opposite edges of the XCKn
signal, ensuring sufficient time for data signals to stabilize. The UCPOLn and UCPHAn function-
ality is summarized in Table 19-2. Note that changing the setting of any of these bits will corrupt
all ongoing communication for both the Receiver and Transmitter.
Table 19-2. UCPOLn and UCPHAn Functionality-
UCPOLn
UCPHAn
SPI Mode
0
0
0
0
1
1
1
0
2
1
1
3
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
Figure 19-1. UCPHAn and UCPOLn data transfer timing diagrams.
UCPOL=0
UCPOL=1
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
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