ATMEGA8U2_14 Datasheet, PDF (269/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
26.7 SPI Timing Characteristics
See Figure 26-3 and Figure 26-7 for details.
Table 26-6. SPI Timing Parameters
Description
Mode
1
SCK period
Master
2
SCK high/low
Master
3
Rise/Fall time
Master
4
Setup
Master
5
Hold
Master
6
Out to SCK
Master
7
SCK to out
Master
8
SCK to out high
Master
9
SS low to out
Slave
10
SCK period
11
SCK high/low⁽¹⁾
Slave
Slave
12
Rise/Fall time
Slave
13
Setup
Slave
14
Hold
Slave
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Min
4 • t_ck
2 • t_ck
10
t_ck
20
20
Typ
Max
See Table 17-5
50% duty cycle
TBD
10
10
0.5 • t_sck
10
10
15
ns
TBD
15
10
Note:
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 t_CLCL for f_CK < 12 MHz
- 3 t_CLCL for f_CK > 12 MHz
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
45
3
MISO
(Data Input)
MSB
...
7
LSB
8
MOSI
(Data Output)
MSB
...
LSB
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