ATMEGA8U2_14 Datasheet, PDF (53/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
While the WDT prescaler allows only even division factors (2, 4, 8...), the WDT peripheral also
includes a clock divider that directly acts on the clock source. This divider handles odd division
factors (3, 5, 7). In combination with the prescaler, a large number of time-out values can be
obtained.
The divider factor change is also ruled by the secure timed sequence : first the WDE and WDCE
bits must be set, and then four cycles are available to load the new divider value into the
WDTCKD register. Be aware that after this operation WDE will still be set. So keep in mind the
importance of order of operations. When setting up the WDT in Interrupt mode with specific val-
ues of prescaler and divider, the divider register must be loaded before the prescaler register :
1. Set WDCE and WDE
2. Load the divider factor into WDTCKD
3. Wait WDCE being automatically cleared (just wait 2 more cycles)
4. Set again WDCE and WDE
5. Clear WDE, set WDIE and load the prescaler factor into WDTCSR in a same operation
6. Now the system is properly configured for Interrupt only mode. Inverting the two opera-
tions would have been resulted into “Reset and Interrupt mode” and needed a third
operation to clear WDE.
The following code example shows one assembly and one C function for turning off the Watch-
dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts
globally) so that no interrupts will occur during the execution of these functions.
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