ATMEGA8U2_14 Datasheet, PDF (16/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
7. AVR Memories
This section describes the different memories in the ATmega8U2/16U2/32U2. The AVR archi-
tecture has two main memory spaces, the Data Memory and the Program Memory space. In
addition, the ATmega8U2/16U2/32U2 features an EEPROM Memory for data storage. All three
memory spaces are linear and regular.
7.1 In-System Reprogrammable Flash Program Memory
The ATmega8U2/16U2/32U2 contains 8K/16K/32K bytes On-chip In-System Reprogrammable
Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash
is organized as 4K x 16, 8K x 16. For software security, the Flash Program memory space is
divided into two sections, Boot Program section and Application Program section.
The Flash memory has an endurance of at least 100,000 write/erase cycles. The
ATmega8U2/16U2/32U2 Program Counter (PC) is 16 bits wide, thus addressing the
8K/16K/32K program memory locations. The operation of Boot Program section and associated
Boot Lock bits for software protection are described in detail in “Memory Programming” on page
246. “Memory Programming” on page 246 contains a detailed description on Flash data serial
downloading using the SPI pins or the debugWIRE interface.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description and ELPM - Extended Load Program Memory
instruction description).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-
ing” on page 12.
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