ATMEGA8U2_14 Datasheet, PDF (209/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Figure 21-5. USB Device Controller Endpoint Interrupt System
Endpoint 4
Endpoint 3
Endpoint 2
Endpoint 1
Endpoint 0
OVERFI
UESTAX.6
UNDERFI
UESTAX.5
NAKINI
UEINTX.6
NAKOUTI
UEINTX.4
RXSTPI
UEINTX.3
RXOUTI
UEINTX.2
STALLEDI
UEINTX.1
TXINI
UEINTX.0
FLERRE
UEIENX.7
NAKINE
UEIENX.6
TXSTPE
UEIENX.4
TXOUTE
UEIENX.3
RXOUTE
UEIENX.2
STALLEDE
UEIENX.1
TXINE
UEIENX.0
EPINT
UEINT.X
Endpoint Interrupt
Processing interrupts are generated when:
• Ready to accept IN data(EPINTx, TXINI=1)
• Received OUT data(EPINTx, RXOUTI=1)
• Received SETUP(EPINTx, RXSTPI=1)
Exception Interrupts are generated when:
• Stalled packet(EPINTx, STALLEDI=1)
• CRC error on OUT in isochronous mode(EPINTx, STALLEDI=1)
• Overflow(EPINTx, OVERFI=1)
• Underflow in isochronous mode(EPINTx, UNDERFI=1)
• NAK IN sent(EPINTx, NAKINI=1)
• NAK OUT sent(EPINTx, NAKOUTI=1)
21.18 Register Description
21.18.1 UDCON – USB Device Control Registers
Bit
7
6
5
4
3
2
1
0
(0xE0)
-
-
-
-
-
RSTCPU RMWKUP DETACH UDCON
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
1
7799D–AVR–11/10
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