ATMEGA8U2_14 Datasheet, PDF (68/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
12.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 12-2. General Digital I/O⁽¹⁾
QD
DDxn
Q _CLR
RESET
PUD
WDx
RDx
Pxn
1
QD
PORTxn
0
Q _CLR
SLEEP
RESET
RRx
WRx
WPx
SYNCHRONIZER
DQ
LQ
DQ
PINxn
Q
RPx
clk _I/O
PUD:
SLEEP:
clk_I/O:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
12.2.1
Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O,
SLEEP, and PUD are common to all ports.
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description for I/O-Ports” on page 82, the DDxn bits are accessed at the DDRx I/O address, the
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
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