ATMEGA8U2_14 Datasheet, PDF (101/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
MAX - 1
MAX
BOTTOM
TOVn
BOTTOM + 1
Figure 15-10 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode and PWM mode, where OCR0A is TOP.
Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 15-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast
PWM mode where OCR0A is TOP.
Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(clk_I/O/8)
TCNTn
(CTC)
OCRnx
TOP - 1
TOP
TOP
BOTTOM
BOTTOM + 1
OCFnx
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