ATMEGA8U2_14 Datasheet, PDF (169/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• Bit 4 – RXENn: Receiver Enable n
Writing this bit to one enables the USART Receiver. The Receiver will override normal port oper-
ation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable n
Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port
operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to
zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size n
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8 n
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8 n
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
18.11.4
UCSRnC – USART Control and Status Register n C
Bit
Read/Write
Initial Value
7
UMSELn1
R/W
0
6
UMSELn0
R/W
0
5
UPMn1
R/W
0
4
UPMn0
R/W
0
3
USBSn
R/W
0
2
UCSZn1
R/W
1
1
UCSZn0
R/W
1
0
UCPOLn
R/W
0
UCSRnC
• Bits 7:6 – UMSELn[1:0] USART Mode Select
These bits select the mode of operation of the USARTn as shown in Table 18-4..
Table 18-4. UMSELn Bits Settings
UMSELn1
UMSELn0
0
0
0
1
1
0
1
1
Mode
Asynchronous USART
Synchronous USART
(Reserved)
Master SPI (MSPIM)⁽¹⁾
Note: 1. See “USART in SPI Mode” on page 176 for full description of the Master SPI Mode (MSPIM)
operation
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
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