ATMEGA8U2_14 Datasheet, PDF (57/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
function of the Watchdog System Reset mode. If the interrupt is not executed before the next
time-out, a System Reset will be applied.
Table 10-1. Watchdog Timer Configuration
WDTON (Fuse)
WDE
WDIE Mode
1 (unprogrammed)
0
0
Stopped
1 (unprogrammed)
0
1
Interrupt Mode
1 (unprogrammed)
1
0
System Reset Mode
1 (unprogrammed)
1
1
Interrupt and System
Reset Mode
0 (programmed)
x
x
System Reset Mode
Action on 2x Time-out
None
Interrupt
Reset
Interrupt, then go to
System Reset Mode
Reset
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-
ditions causing failure, and a safe start-up after the failure.
• Bit 5, 2:0 - WDP[3:0]: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table on page 58.
10.5.3
WDTCKD – Watchdog Timer Clock Divider Register
Bit
7
(0x62)
-
Read/Write
R
Initial Value
0
6
5
4
-
WDEWIF- WCLKD2
CM
R
R/W
R/W
0
0
0
3
WDEWIF
R/W
0
2
WDEWIE
R/W
0
1
WCLKD1
R/W
0
0
WCLKD0
R/W
0
WDTCKD
• Bit 7:6 - Res: Reserved bits
These bits are reserved and will always read as zero.
• Bit 5 - WDEWIFCL: Watchdog Early Warning Flag Clear Mode
When this bit has been set by software, the WDEWIF interrupt flag is not cleared by hardware
when entering the Watchdog Interrupt subroutine (it has to be cleared by software by writing a
logic one to the flag).
When cleared, the WDEWIF is cleared by hardware when executing the corresponding interrupt
handling vector.
• Bit 4 - WCLKD2 bit: Watchdog Timer Clock Divider
See “Bit 1:0 - WCLKD[1:0]: Watchdog Timer Clock Divider” on page 58.
57
7799D–AVR–11/10