ATMEGA8U2_14 Datasheet, PDF (211/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• Bit 4 – WAKEUPI: Wake-up CPU Interrupt Flag
This flag is set by hardware when the USB controller detects a non-idle signal from the USB
lines. This WAKEUPI flag can generate a “USB general interrupt” if WAKEUPE bit is set. Writing
this bit to zero acknowledges the interrupt source. Writing this bit to one has no effect.Shall be
cleared by software. Setting by software has no effect.
See “Suspend, Wake-up and Resume” on page 200 for more details.
• Bit 3 – EORSTI: End Of Reset Interrupt Flag
This flag is set by hardware when the USB controller detects an “End Of Reset” event on the
USB lines. has been detected by the USB controller. This EORSTI flag can generate a “USB
general interrupt” if EORSTE bit is set. Writing this bit to zero acknowledges the interrupt source
(USB clocks must be enabled before). Writing this bit to one has no effect.
Shall be cleared by software. Setting by software has no effect.
• Bit 2 – SOFI: Start Of Frame Interrupt Flag
This flag is set by hardware when the USB controller detects a Start Of Frame PID (SOF) on the
USB lines. This SOFI flag can generate a “USB general interrupt” if SOFE bit is set. Writing this
bit to zero acknowledges the interrupt source (USB clocks must be enabled before). Writing this
bit to one has no effect.
• Bit 1 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 0 – SUSPI: Suspend Interrupt Flag
This flag is set by hardware when the USB controller detects a suspend state on the bus (idle
state for more than 3ms). This SUSPI flag can generate a USB general interrupt if SUSPE bit is
set. Writing this bit to zero acknowledges the interrupt source (USB clocks must be enabled
before). Writing this bit to one has no effect.
See “Suspend, Wake-up and Resume” on page 200 for more details.
The interrupt flag bits are set even if their corresponding ‘Enable’ bits is not set.
21.18.3 UDIEN – USB Device Interrupt Enable Register
Bit
7
6
5
4
3
2
(0xE2)
-
UPRSME EORSME WAKEUPE EORSTE
SOFE
Read/Write
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
1
0
-
SUSPE UDIEN
R
R/W
0
0
• Bit 7 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 6 – UPRSME: Upstream Resume Interrupt Enable Bit
Writing this bit to one enables interrupt on UPRSMI flag. An Upstream resume interrupt will be
generated only if the UPRSME bit is set to one, the Global Interrupt Flag in SREG is written to
one and the UPRSMI bit is set.
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