ATMEGA8U2_14 Datasheet, PDF (87/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• Bit 1:0 – PCIF[1:0]: Pin Change Interrupt Flag 1:0
When a logic change on any PCINT[12:8]/[7:0] pin triggers an interrupt request, PCIF1/0
becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in EIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
13.2.7
PCMSK0 – Pin Change Mask Register 0
Bit
(0x6B)
Read/Write
Initial Value
7
PCINT7
R/W
0
6
PCINT6
R/W
0
5
PCINT5
R/W
0
4
PCINT4
R/W
0
3
PCINT3
R/W
0
2
PCINT2
R/W
0
1
PCINT1
R/W
0
0
PCINT0
R/W
0
PCMSK0
• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
13.2.8
PCMSK1 – Pin Change Mask Register 1
Bit
7
6
(0x6C)
-
-
Read/Write
R
R
Initial Value
0
0
5
4
3
2
1
0
-
PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
• Bit 4:0 – PCINT[12:8]: Pin Change Enable Mask 12:8
Each PCINT[12:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[12:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[12:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
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