ATMEGA8U2_14 Datasheet, PDF (82/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
12.4 Register Description for I/O-Ports
12.4.1 MCUCR – MCU Control Register
Bit
7
6
0x35 (0x55)
JTD
–
Read/Write
R/W
R
Initial Value
0
0
5
4
3
2
1
0
–
PUD
–
–
IVSEL
IVCE MCUCR
R
R/W
R
R
R/W
R/W
0
0
0
0
0
0
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-
figuring the Pin” on page 68 for more details about this feature.
12.4.2
PORTB – Port B Data Register
Bit
0x05 (0x25)
Read/Write
Initial Value
7
PORTB7
R/W
0
6
PORTB6
R/W
0
5
PORTB5
R/W
0
4
PORTB4
R/W
0
3
PORTB3
R/W
0
2
PORTB2
R/W
0
1
PORTB1
R/W
0
0
PORTB0
R/W
0
PORTB
12.4.3
DDRB – Port B Data Direction Register
Bit
0x04 (0x24)
Read/Write
Initial Value
7
DDB7
R/W
0
6
DDB6
R/W
0
5
DDB5
R/W
0
4
DDB4
R/W
0
3
DDB3
R/W
0
2
DDB2
R/W
0
1
DDB1
R/W
0
0
DDB0
R/W
0
DDRB
12.4.4
PINB – Port B Input Pins Address
Bit
0x03 (0x23)
Read/Write
Initial Value
7
PINB7
R/W
N/A
6
PINB6
R/W
N/A
5
PINB5
R/W
N/A
4
PINB4
R/W
N/A
3
PINB3
R/W
N/A
2
PINB2
R/W
N/A
1
PINB1
R/W
N/A
0
PINB0
R/W
N/A
PINB
12.4.5 PORTC – Port C Data Register
Bit
7
6
5
4
3
2
1
0
0x08 (0x28) PORTC7 PORTC6 PORTC5 PORTC4
-
PORTC2 PORTC1 PORTC0 PORTC
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
12.4.6 DDRC – Port C Data Direction Register
Bit
7
6
5
4
3
2
1
0
0x07 (0x27)
DDC7
DDC6
DDC5
DDC4
-
DDC2
DDC1
DDC0 DDRC
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
12.4.7 PINC – Port C Input Pins Address
Bit
7
6
5
4
3
2
1
0
0x06 (0x26)
PINC7
PINC6
PINC5
PINC4
-
PINC2
PINC1
PINC0 PINC
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
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