ATMEGA8U2_14 Datasheet, PDF (151/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 18-1 contains equations for calculating the baud rate (in bits per second) and for calculat-
ing the UBRRn value for each mode of operation using an internally generated clock source.
Table 18-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating Baud Rate⁽¹⁾
Equation for Calculating UBRR Value
UBRRn = -------^f---^O----^S--^C------- – 1
16 B A U D
Asynchronous Normal mode
(U2Xn = 0)
BAUD
=
----------------^f---^O----^S--^C----------------
16UBRRn + 1
Asynchronous Double Speed
mode (U2Xn = 1)
BAUD = --------------^f---^O----^S---^C--------------
8UBRRn + 1
Synchronous Master mode
BAUD = --------------^f---^O----^S---^C--------------
2UBRRn + 1
UBRRn = -----^f---^O----^S---^C----- – 1
8BAUD
UBRRn = -----^f---^O----^S---^C----- – 1
2BAUD
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
Baud rate (in bits per second, bps)
f_OSC
UBRRn
System Oscillator clock frequency
Contents of the UBRRHn and UBRRLn Registers, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 18-9 on
page 172.
18.3.2
Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has
effect for the asynchronous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling
the transfer rate for asynchronous communication. Note however that the Receiver will in this
case only use half the number of samples (reduced from 16 to 8) for data sampling and clock
recovery, and therefore a more accurate baud rate setting and system clock are required when
this mode is used. For the Transmitter, there are no downsides.
7799D–AVR–11/10
151