ATMEGA8U2_14 Datasheet, PDF (104/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 15-4 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to phase
correct PWM mode.
Table 15-7.
COM0B1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode⁽¹⁾
COM0B0 Description
0
Normal port operation, OC0B disconnected.
1
Reserved
0
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 99 for more details.
• Bits 3:2 – Res: Reserved Bits
These bits are reserved and will always read as zero.
• Bits 1:0 – WGM0[1:0]: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 15-8. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 96).
Table 15-8. Waveform Generation Mode Bit Description
Mode
WGM2
WGM1
WGM0
Timer/Counter
Mode of
Operation
TOP
0
0
0
0
Normal
0xFF
1
0
0
1
PWM, Phase
Correct
0xFF
2
0
1
0
CTC
OCRA
3
0
1
1
Fast PWM
0xFF
4
1
0
0
Reserved
–
5
1
0
1
PWM, Phase
Correct
OCRA
6
1
1
0
Reserved
–
7
1
1
1
Fast PWM
OCRA
Update of
OCRx at
Immediate
TOP
Immediate
TOP
–
TOP
–
TOP
TOV Flag
Set on⁽¹⁾⁽²⁾
MAX
BOTTOM
MAX
MAX
–
BOTTOM
–
TOP
Notes: 1. MAX = 0xFF
2. BOTTOM = 0x00
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