ATMEGA8U2_14 Datasheet, PDF (106/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 15-9. Clock Select Bit Description (Continued)
CS02 CS01 CS00 Description
1
0
0
clk_I/O/256 (From prescaler)
1
0
1
clk_I/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
15.9.3
TCNT0 – Timer/Counter Register
Bit
0x26 (0x46)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
TCNT0[7:0]
TCNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
15.9.4
OCR0A – Output Compare Register A
Bit
0x27 (0x47)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR0A[7:0]
OCR0A
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0A pin.
15.9.5
OCR0B – Output Compare Register B
Bit
0x28 (0x48)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR0B[7:0]
OCR0B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC0B pin.
15.9.6 TIMSK0 – Timer/Counter Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
(0x6E)
–
–
–
–
–
OCIE0B OCIE0A TOIE0 TIMSK0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:3 – Res: Reserved Bits
These bits are reserved bits and will always read as zero.
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