ATMEGA8U2_14 Datasheet, PDF (76/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
.Table 12-4 and Table 12-5 relate the alternate functions of Port B to the overriding signals
shown in Figure 12-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT..
Table 12-4. Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PB7/OC0A/OC1C/
PCINT7
PB6/PCINT6
PB5/PCINT5
PUOE 0
0
0
PUOV 0
0
0
DDOE 0
0
0
DDOV 0
0
0
PVOE OC0A/OC1C ENABLE 0
0
PVOV OC0A/OC1C
0
0
DIEOE PCINT7 • PCIE0
PCINT6 • PCIE0
PCINT5 • PCIE0
DIEOV 1
1
1
DI
PCINT7 INPUT
PCINT6 INPUT
PCINT5 INPUT
AIO
–
–
–
PB4/T1/PCINT4
0
0
0
0
0
0
PCINT4 • PCIE0
1
PCINT4 INPUT
T1 INPUT
–
Table 12-5. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name
PB3/MISO/PCINT3/
PDO
PB2/MOSI/PCINT2/
PDI
PB1/SCK/
PCINT1
PUOE SPE • MSTR
SPE • MSTR
SPE • MSTR
PUOV PORTB3 • PUD
PORTB2 • PUD
PORTB1 • PUD
DDOE SPE • MSTR
SPE • MSTR
SPE • MSTR
DDOV 0
0
0
PVOE SPE • MSTR
SPE • MSTR
SPE • MSTR
PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT
DIEOE PCINT3 • PCIE0
PCINT2 • PCIE0
PCINT1 • PCIE0
DIEOV 1
1
1
SPI MSTR INPUT
SPI SLAVE INPUT
SCK INPUT
DI
PCINT3 INPUT
PCINT2 INPUT
PCINT1 INPUT
AIO
–
–
–
PB0/SS/PCINT0
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
PCINT0 • PCIE0
1
SPI SS
PCINT0 INPUT
–
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