ATMEGA8U2_14 Datasheet, PDF (108/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
16. 16-bit Timer/Counter 1 with PWM
16.1 Features
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Three independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Five independent interrupt sources (TOV1, OCF1A, OCF1B, OCF1C, ICF1)
16.2 Overview
The 16-bit Timer/Counter 1 unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. Most register and bit references in this sec-
tion are written in general form. A lower case “n” replaces the Timer/Counter number (for this
product, only n=1 is available), and a lower case “x” replaces the Output Compare unit channel.
However, when using the register or bit defines in a program, the precise form must be used,
i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 16-1. For the actual
placement of I/O pins, see “Pinout” on page 2. CPU accessible I/O Registers, including I/O bits
and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in
the “16-bit Timer/Counter 1 with PWM” on page 108.
The Power Reduction Timer/Counter1 bit, PRTIM1, in “PRR0 – Power Reduction Register 0” on
page 46 must be written to zero to enable Timer/Counter1 module.
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