ATMEGA8U2_14 Datasheet, PDF (60/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 10-5. Watchdog Timer Prescale Select, DIV = 2 (CLKwdt = CLK128 / 5)
WDP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
WDP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WDP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WDP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Number of WDT Oscillator
Cycles before 1st time-out
(Early warning)
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
Early warning Typical
Time-out at
V_CC = 5.0V
80 ms
160 ms
320 ms
0.625 s
1.25 s
2.5 s
5s
10 s
20 s
40 s
Reserved
Watchdog
Reset/Interrupt Typical
Time-out at
V_CC = 5.0V
160 ms
320 ms
640 ms
1.25 s
2.5 s
5s
10 s
20 s
40 s
80 s
Table 10-6. Watchdog Timer Prescale Select, DIV = 3 (CLKwdt = CLK128 / 7)
WDP3
0
0
0
0
0
0
0
0
1
1
WDP2
0
0
0
0
1
1
1
1
0
0
WDP1
0
0
1
1
0
0
1
1
0
0
WDP0
0
1
0
1
0
1
0
1
0
1
Number of WDT Oscillator
Cycles before 1st time-out
(Early warning)
2K (2048) cycles
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
Early warning Typical
Time-out at
V_CC = 5.0V
112 ms
224 ms
448 ms
0.875 s
1.75 s
3.5 s
7s
14 s
28 s
56 s
Watchdog
Reset/Interrupt Typical
Time-out at
V_CC = 5.0V
224 ms
448 ms
896 ms
1.75 s
3.5 s
7s
14 s
28 s
56 s
112 s
60
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