ATMEGA8U2_14 Datasheet, PDF (88/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
14. Timer/Counter0 and Timer/Counter1 Prescalers
14.1 Overview
Timer/Counter0 and 1 share the same prescaler module, but the Timer/Counters can have dif-
ferent prescaler settings. The description below applies to all Timer/Counters. Tn is used as a
general name, n = 0 or 1.
14.2
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn[2:0] = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used
as a clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64,
f_{CLK_I/O}/256, or f_{CLK_I/O}/1024.
14.3
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by
the Timer/Counter’s clock select, the state of the prescaler will have implications for situations
where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is
enabled and clocked by the prescaler (6 > CSn[2:0] > 1). The number of system clock cycles
from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock
cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
14.4
External Clock Source
An external clock source applied to the Tn pin can be used as Timer/Counter clock (clk_Tn). The
Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-
nized (sampled) signal is then passed through the edge detector. Figure 14-1 shows a functional
equivalent block diagram of the Tn synchronization and edge detector logic. The registers are
clocked at the positive edge of the internal system clock (clk_I/O). The latch is transparent in the
high period of the internal system clock.
The edge detector generates one clk_Tn pulse for each positive (CSn2:0 = 7) or negative (CSn2:0
= 6) edge it detects.
Figure 14-1. Tn/T0 Pin Sampling
Tn
clk_I/O
DQ
LE
DQ
Synchronization
DQ
Tn_sync
(To Clock
Select Logic)
Edge Detector
88
7799D–AVR–11/10