ATMEGA8U2_14 Datasheet, PDF (40/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 8-9.
CLKPS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Clock Prescaler Select
CLKPS2
CLKPS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
CLKPS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock Division Factor
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8.11.6 PLLCSR – PLL Control and Status Register
Bit
7
6
5
0x29 (0x49)
–
–
–
Read/Write
R
R
R
Initial Value
0
0
0
4
DIV5
R/W
0
3
DIV3
R
0
2
PINDIV
R
0
1
PLLE
R/W
0
0
PLOCK
R
0
PLLCSR
• Bit 7:5 – Res: Reserved Bits
These bits are reserved bits in the ATmega8U2/16U2/32U2 and always read as zero.
• Bit 4 – DIV5 PLL Input Prescaler (1:5)
• Bit 3 – DIV3 PLL Input Prescaler (1:3)
• Bit 2 – PINDIV PLL Input Prescaler (1:1, 1:2)
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the
PLL from either a 8 or 16 MHz input.
When using a 8 MHz clock source, this bit must be set to 0 before enabling PLL (1:1).
When using a 16 MHz clock source, this bit must be set to 1 before enabling PLL (1:2).
• Bit 3:2 – Res: Reserved Bits
These bits are reserved and always read as zero.
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