ATMEGA8U2_14 Datasheet, PDF (81/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 12-10. Overriding Signals for Alternate Functions PD7..PD4
Signal Name
PD7/T0/INT7/ PD6/INT6/
HBW/CTS
RTS
PD5/XCK/PCINT12
PUOE
CTS
RTS
0
PUOV
PORTD7 •
PUD
0
0
DDOE
CTS
RTS
0
DDOV
0
1
0
PVOE
0
RTS
OUTPUT
ENABLE
XCK OUTPUT ENABLE
PVOV
0
RTS
OUTPUT
XCK1 OUTPUT
DIEOE
INT7/CTS
ENABLE
INT6
ENABLE
PCINT12 ENABLE
DIEOV
1
1
1
T0 INPUT
XCK INPUT
DI
INT7 INPUT INT6 INPUT
PCINT12 INPUT
CTS INPUT
AIO
–
–
–
PD4/INT5
0
0
0
0
0
0
INT5
ENABLE
1
INT5 INPUT
–
Table 12-11. Overriding Signals for Alternate Functions in PD3..PD0⁽¹⁾
Signal Name
PD3/INT3/TXD1
PD2/INT2/RXD1/
AIN1
PD1/INT1/AIN0 PD0/INT0/OC0B
PUOE
TXEN1
RXEN1
0
0
PUOV
0
PORTD2 • PUD
0
0
DDOE
TXEN1
RXEN1
0
0
DDOV
1
0
0
0
PVOE
TXEN1
0
0
OC0B ENABLE
PVOV
TXD1
0
0
OC0B
DIEOE
INT3 ENABLE
INT2 ENABLE
AIN1 ENABLE
INT1 ENABLE
AIN0 ENABLE
INT0 ENABLE
DIEOV
1
AIN1 ENABLE
AIN0 ENABLE
1
DI
INT3 INPUT
INT2 INPUT/RXD1 INT1 INPUT
INT0 INPUT
AIO
–
AIN1 INPUT
AIN0 INPUT
–
Note:
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure.
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