ATMEGA8U2_14 Datasheet, PDF (225/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 22-1.
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ACIS0
Interrupt Mode
0
Comparator Interrupt on Output Toggle.
1
Reserved
0
Comparator Interrupt on Falling Output Edge.
1
Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
22.2.2 ACMUX – Analog Comparator Input Multiplexer
Bit
7
6
5
4
3
2
1
0
(0x7D)
–
–
–
–
–
CMUX2 CMUX1 CMUX0 ACMUX
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
• Bit 2, 0 – CMUX2:0: Analog Comparator Selection Bits
The value of these bits selects which combination of analog inputs are connected to the analog
comparator.
The different settings are shown in Table 22-2.
Table 22-2.
CMUX2
0
0
0
0
1
1
1
1
CMUX2:0 Settings
CMUX1
CMUX0
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Comparator Input
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
Reserved
Reserved
22.2.3
DIDR1 – Digital Input Disable Register 1
Bit
Read/Write
Initial Value
7
6
–
AIN6D
R
R/W
0
0
5
AIN5D
R/W
0
4
AIN4D
R/W
0
3
AIN3D
R/W
0
2
AIN2D
R/W
0
1
AIN1D
R/W
0
0
AIN0D
R/W
0
DIDR1
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AINx pin is disabled. The corre-
sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-
ten logic one to reduce power consumption in the digital input buffer.
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