ATMEGA8U2_14 Datasheet, PDF (222/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
This register contains the number of received byte into the current bank of the selected end-
point. The content of this register is decremented after each write access to the endpoint data
register.
21.18.19 UEINT – USB Endpoint Number interrupt Register
Bit
7
6
5
4
3
2
1
0
(0xF4)
-
-
-
EPINT4:0
UEINT
Read/Write
R
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:5 – Res: Reserved
The value read from these bits is always 0. Do not set these bits.
• Bits 4:0 – EPINT[4:0]: Endpoint Interrupts Bits
These flags are updated by the USB controller when a USB endpoint interrupt occurs (at least
one bit in UEINTX set). Each bit in this field indicates which endpoint number has generated a
USB endpoint interrupt request. Each one of these bits are independently cleared by hardware
when their respective interrupt source is served.
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