ATMEGA8U2_14 Datasheet, PDF (195/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
• Be sure to have interrupts enabled (WAKEUPE) to exit sleep mode
• Put the MCU in sleep mode
Resuming the USB interface
• Enable PLL
• Wait PLL lock
• Clear USB suspend clock
• Clear Resume information
20.10 Registers Description
20.10.1 USBCON – USB General Control Registers
Bit
7
6
5
4
3
2
1
0
(0xD8)
USBE
-
FRZLK
-
-
-
-
-
USBCON
Read/Write
R/W
R
R/W
R
R
R
R
R
Initial Value
0
0
1
0
0
0
0
0
• Bit 7 – USBE: USB macro Enable Bit
Writing this bit to one enables the USB controller and the USB data buffers (D+ and D-). Clear-
ing this bit disables the USB controller and buffers. When cleared the USB controller is reset.
• Bit 6 – Res: Reserved
This bit is reserved and should always read as zero.
• Bit 5 – FRZCLK: Freeze USB Clock Bit
Writing this bit to one disables the internal clock for the USB controller, and tehreby freezing it.
Activating this mode reduces power consumption. All the USB flags are kept unchanged. Only
the “Resume detection” is still active in this mode.
Writing this bit to zero unfreezes the USB controller and allows full operation of the USB
interface.
• Bits 4:0 – Res: Reserved
These bits are reserved and should always read as zero.
20.10.2 UPOE – USB Software Output Enable register
Bit
7
6
5
4
3
(0xFB)
UPWE1 UPWE0 UPDRV1 UPDRV0
-
Read/Write
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
2
1
0
-
DPI
DMI
UPOE
R
R
R
0
0
0
• Bit 7:6 – UPWE[1:0]: USB Buffers Direct Drive enable configuration
These bits select the mode of operation of the USB buffers according to Table 20-2. The possi-
ble configurations of these bits allows to enable or disable the USB buffers direct drive by soft-
ware. When direct drive for USB buffers is enable, the UPDRV[1:0] values are output to the
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