ATMEGA8U2_14 Datasheet, PDF (78/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

7799D–AVR–11/10
ATmega8U2/16U2/32U2
Reset, Reset input. External Reset input is active low and enabled by unprogramming ("1") the
RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the
pin is used as the RESET pin.
dW, debugWire channel. When the debugWIRE Enable (DWEN) Fuse is programmed and Lock
bits are unprogrammed, the debugWIRE system within the target device is activated. The
RESET port pin is configured as a wired -AND (open-drain) bi-directional I/O pin with pull-up
enabled and becomes the communication gateway between the target and the emulator.
• XTAL2, Bit 0
XTAL2, Oscillator. The PC0 pin can serve as Inverting Output for internal Oscillator amplifier.
Table 12-7 and Table 12-8 relate the alternate functions of Port C to the overriding signals
shown in Figure 12-5 on page 72.
Table 12-7. Overriding Signals for Alternate Functions in PC7..PC4
Signal
Name
PC6/PCINT8/
PC7/ICP1/INT4/CLK0 OC1A
PC5/PCINT9/
OC1B
PUOE
0
0
0
PUOV
0
0
0
DDOE
0
0
0
DDOV
0
0
0
PVOE
0
OC1A ENABLE
OC1B ENABLE
PVOV
0
OC1A
OC1B
DIEOE INT4 ENABLE
PCINT8 ENABLE PCINT9 ENABLE
DIEOV 1
1
1
DI
INT4 INPUT
PCINT8 INPUT
PCINT9 INPUT
AIO
–
–
–
PC4/PCINT10
0
0
0
0
0
0
PCINT10 ENABLE
1
PCINT10 INPUT
–
Table 12-8.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Overriding Signals for Alternate Functions in PC2..PC0
PC2/PCINT11
0
0
0
0
0
0
PCINT11 ENABLE
1
PCINT11 INPUT
–
PC1/RESET/dW
0
0
0
0
0
0
0
0
–
–
PC0/XTAL2
0
0
0
0
0
0
0
0
–
–
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