ATMEGA8U2_14 Datasheet, PDF (130/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
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Table 16-1. Compare Output Mode, non-PWM
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC
disconnected.
0
1
Toggle OCnA/OCnB/OCnC on compare match.
1
0
Clear OCnA/OCnB/OCnC on compare match
(set output to low level).
1
1
Set OCnA/OCnB/OCnC on compare match (set
output to high level).
Table 16-2 shows the COMnx[1:0] bit functionality when the WGMn[3:0] bits are set to the fast
PWM mode.
Table 16-2. Compare Output Mode, Fast PWM
COMnA1/COMnB1/
COMnC0
COMnA0/COMnB0/
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC
disconnected.
WGM1[3:0] = 14 or 15: Toggle OC1A on
Compare Match, OC1B and OC1C disconnected
0
1
(normal port operation). For all other WGM1
settings, normal port operation,
OC1A/OC1B/OC1C disconnected.
1
0
Clear OCnA/OCnB/OCnC on compare match,
set OCnA/OCnB/OCnC at TOP
1
1
Set OCnA/OCnB/OCnC on compare match,
clear OCnA/OCnB/OCnC at TOP
Note:
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear
is done at TOP. See “Fast PWM Mode” on page 97. for more details.
Table 16-3 shows the COMnx[1:0] bit functionality when the WGMn[3:0] bits are set to the phase
correct and frequency correct PWM mode.
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