ATMEGA8U2_14 Datasheet, PDF (272/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 26-9. Parallel Programming Characteristics, V_CC = 5V ± 10% (Continued)
Symbol
Parameter
Min Typ Max
Units
t_XLWL
XTAL1 Low to WR Low
0
ns
t_XLPH
XTAL1 Low to PAGEL high
0
ns
t_PLXH
PAGEL low to XTAL1 high
150
ns
t_BVPH
BS1 Valid before PAGEL High
67
ns
t_PHPL
PAGEL Pulse Width High
150
ns
t_PLBX
BS1 Hold after PAGEL Low
67
ns
t_WLBX
BS2/1 Hold after WR Low
67
ns
t_PLWL
PAGEL Low to WR Low
67
ns
t_BVWL
BS2/1 Valid to WR Low
67
ns
t_WLWH
WR Pulse Width Low
150
ns
t_WLRL
WR Low to RDY/BSY Low
0
t_WLRH
WR Low to RDY/BSY High⁽¹⁾
3.7
t_{WLRH_CE}
WR Low to RDY/BSY High for Chip Erase⁽²⁾
7.5
1
s
4.5
ms
9
ms
t_XLOL
XTAL1 Low to OE Low
0
ns
t_BVDV
BS1 Valid to DATA valid
0
250
ns
t_OLDV
OE Low to DATA Valid
250
ns
t_OHDZ
OE High to DATA Tri-stated
250
ns
Notes: 1. t_WLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. t_{WLRH_CE} is valid for the Chip Erase command.
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