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| ATMEGA8U2_14 Datasheet, PDF (293/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution | |||
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Mnemonics
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
MOV
MOVW
LDI
LD
LD
LD
LD
LD
LD
LDD
LD
LD
LD
LDD
LDS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
STS
LPM
LPM
LPM
SPM
IN
OUT
PUSH
POP
NOP
SLEEP
WDR
BREAK
Operands
Description
Rd
Rotate Left Through Carry
Rd
Rotate Right Through Carry
Rd
Arithmetic Shift Right
Rd
Swap Nibbles
s
Flag Set
s
Flag Clear
Rr, b
Bit Store from Register to T
Rd, b
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS
Rd, Rr
Move Between Registers
Rd, Rr
Copy Register Word
Rd, K
Load Immediate
Rd, X
Load Indirect
Rd, X+
Load Indirect and Post-Inc.
Rd, - X
Load Indirect and Pre-Dec.
Rd, Y
Load Indirect
Rd, Y+
Load Indirect and Post-Inc.
Rd, - Y
Load Indirect and Pre-Dec.
Rd,Y+q
Load Indirect with Displacement
Rd, Z
Load Indirect
Rd, Z+
Load Indirect and Post-Inc.
Rd, -Z
Load Indirect and Pre-Dec.
Rd, Z+q
Load Indirect with Displacement
Rd, k
Load Direct from SRAM
X, Rr
Store Indirect
X+, Rr
Store Indirect and Post-Inc.
- X, Rr
Store Indirect and Pre-Dec.
Y, Rr
Store Indirect
Y+, Rr
Store Indirect and Post-Inc.
- Y, Rr
Store Indirect and Pre-Dec.
Y+q,Rr
Store Indirect with Displacement
Z, Rr
Store Indirect
Z+, Rr
Store Indirect and Post-Inc.
-Z, Rr
Store Indirect and Pre-Dec.
Z+q,Rr
Store Indirect with Displacement
k, Rr
Store Direct to SRAM
Load Program Memory
Rd, Z
Load Program Memory
Rd, Z+
Load Program Memory and Post-Inc
Store Program Memory
Rd, P
In Port
P, Rr
Out Port
Rr
Push Register on Stack
Rd
Pop Register from Stack
MCU CONTROL INSTRUCTIONS
No Operation
Sleep
Watchdog Reset
Break
7799DâAVRâ11/10
ATmega8U2/16U2/32U2
Operation
Rd(0)ï¬C,Rd(n+1)ï¬ Rd(n),Cï¬Rd(7)
Rd(7)ï¬C,Rd(n)ï¬ Rd(n+1),Cï¬Rd(0)
Rd(n) ï¬ Rd(n+1), n=0..6
Rd(3..0)ï¬Rd(7..4),Rd(7..4)ï¬Rd(3..0)
SREG(s) ï¬ 1
SREG(s) ï¬ 0
T ï¬ Rr(b)
Rd(b) ï¬ T
Cï¬1
Cï¬0
Nï¬1
Nï¬0
Zï¬1
Zï¬0
Iï¬1
Iï ï¬ 0
Sï¬1
Sï¬0
Vï¬1
Vï¬0
Tï¬1
Tï¬0
Hï¬1
Hï¬0
Rd ï¬ Rr
Rd+1:Rd ï¬ Rr+1:Rr
Rd ï¬ K
Rd ï¬ (X)
Rd ï¬ (X), X ï¬ X + 1
X ï¬ X - 1, Rd ï¬ (X)
Rd ï¬ (Y)
Rd ï¬ (Y), Y ï¬ Y + 1
Y ï¬ Y - 1, Rd ï¬ (Y)
Rd ï¬ (Y + q)
Rd ï¬ (Z)
Rd ï¬ (Z), Z ï¬ Z+1
Z ï¬ Z - 1, Rd ï¬ (Z)
Rd ï¬ (Z + q)
Rd ï¬ (k)
(X)ï ï¬ Rr
(X)ï ï¬ Rr, X ï¬ X + 1
X ï¬ X - 1, (X) ï¬ Rr
(Y) ï¬ Rr
(Y) ï¬ Rr, Y ï¬ Y + 1
Y ï¬ Y - 1, (Y) ï¬ Rr
(Y + q) ï¬ Rr
(Z) ï¬ Rr
(Z) ï¬ Rr, Z ï¬ Z + 1
Z ï¬ Z - 1, (Z) ï¬ Rr
(Z + q) ï¬ Rr
(k) ï¬ Rr
R0 ï¬ (Z)
Rd ï¬ (Z)
Rd ï¬ (Z), Z ï¬ Z+1
(Z) ï¬ R1:R0
Rd ï¬ P
P ï¬ Rr
STACK ï¬ Rr
Rd ï¬ STACK
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
For On-chip Debug Only
Flags
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
#Clocks
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
1
1
2
2
1
1
1
N/A
293
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