ATMEGA8U2_14 Datasheet, PDF (203/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
21.12.2
Control Read
The next figure shows a control read transaction. The USB controller has to manage the simulta-
neous write requests from the CPU and the USB host:
A NAK handshake is always generated at the first status stage command.
When the controller detect the status stage, all the data written by the CPU are erased, and
clearing TXINI has no effects.
The firmware checks if the transmission is complete or if the reception is complete.
The OUT retry is always ACK'ed. This reception:
- set the RXOUTI flag (received OUT data)
- set the TXINI flag (data sent, ready to accept new data)
software algorithm:
set transmit ready
wait (transmit complete OR Receive complete)
if receive complete, clear flag and return
if transmit complete, continue
Once the OUT status stage has been received, the USB controller waits for a SETUP request.
The SETUP request have priority over any other request and has to be ACK’ed. This means that
any other flag should be cleared and the fifo reset when a SETUP is received.
WARNING: the byte counter is reset when a OUT Zero Length Packet is received. The firmware
has to take care of this.
21.13 OUT endpoint management
OUT packets are sent by the host. All the data can be read by the CPU, which acknowledges or
not the bank when it is empty.
21.13.1 Overview
The Endpoint must be configured first.
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