ATMEGA8U2_14 Datasheet, PDF (2/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

1. Pin Configurations
Figure 1-1. Pinout
ATmega8U2/16U2/32U2
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11 / AIN2 ) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
5
QFN32
21
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
XTAL1
(PC0) XTAL2
GND
VCC
(PCINT11 /AIN2 ) PC2
(OC.0B / INT0) PD0
(AIN0 / INT1) PD1
(RXD1 / AIN1 / INT2) PD2
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
5
TQFP32
21
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
Reset (PC1 / dW)
PC6 (OC.1A / PCINT8)
PC7 (INT4 / ICP1 / CLKO)
PB7 (PCINT7 / OC.0A / OC.1C)
PB6 (PCINT6)
PB5 (PCINT5)
PB4 (T1 / PCINT4)
PB3 (PDO / MISO / PCINT3)
Note: The large center pad underneath the QFN package should be soldered to ground on the board to
ensure good mechanical stability.
1.1 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2
7799E–AVR–09/2012