ATMEGA8U2_14 Datasheet, PDF (103/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

7799D–AVR–11/10
ATmega8U2/16U2/32U2
Table 15-4 shows the COM0A1:0 bit functionality when the WGM0[2:0] bits are set to phase cor-
rect PWM mode.
Table 15-4.
COM0A1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode⁽¹⁾
COM0A0 Description
0
Normal port operation, OC0A disconnected.
1
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
0
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
1
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 99 for more details.
• Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B[1:0]
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B[1:0] bits depends on the
WGM0[2:0] bit setting. Table 15-2 shows the COM0A[1:0] bit functionality when the WGM0[2:0]
bits are set to a normal or CTC mode (non-PWM).
[
Table 15-5. Compare Output Mode, non-PWM Mode
COM0B1
COM0B0 Description
0
0
Normal port operation, OC0B disconnected.
0
1
Toggle OC0B on Compare Match
1
0
Clear OC0B on Compare Match
1
1
Set OC0B on Compare Match
Table 15-3 shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast
PWM mode.
Table 15-6.
COM0B1
0
0
1
1
Compare Output Mode, Fast PWM Mode⁽¹⁾
COM0B0 Description
0
Normal port operation, OC0B disconnected.
1
Reserved
0
Clear OC0B on Compare Match, set OC0B at TOP
1
Set OC0B on Compare Match, clear OC0B at TOP
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 97
for more details.
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