ATMEGA8U2_14 Datasheet, PDF (270/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

ATmega8U2/16U2/32U2
Table 26-7. SPI Interface Timing Requirements (Slave Mode)
SS
9
SCK
(CPOL = 0)
SCK
(CPOL = 1)
13
14
MOSI
(Data Input)
MSB
...
15
MISO
(Data Output)
MSB
...
10
16
11
11
12
LSB
17
LSB
X
26.8 Hardware Boot EntranceTiming Characteristics
Figure 26-4. Hardware Boot Timing Requirements
RESET
ALE/HWB
t_SHRH
t_HHRH
Table 26-8. Hardware Boot Timings
Symbol Parameter
tSHRH
HWB low Setup before Reset High
tHHRH
HWB low Hold after Reset High
Min
0
StartUpTime(SUT) +
Time Out Delay(TOUT)
Max
26.9 Parallel Programming Characteristics
Figure 26-5. Parallel Programming Timing, Including some General Timing Requirements
XTAL1
Data & Contol
(DATA, XA0/1, BS1, BS2)
PAGEL
WR
t_DVXH
t_XHXL
t_XLWL
t_XLDX
t_BVPH
t_PHPL
t_PLBX t _BVWL
t_PLWL
t_WLWH
WLRL
t_WLBX
RDY/BSY
t_WLRH
7799D–AVR–11/10
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