ATMEGA8U2_14 Datasheet, PDF (170/310 Pages) ATMEL Corporation – 125 Powerful Instructions – Most Single Clock Cycle Execution

7799D–AVR–11/10
ATmega8U2/16U2/32U2
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
Table 18-5. UPMn Bits Settings
UPMn1
UPMn0
0
0
0
1
1
0
1
1
Parity Mode
Disabled
Reserved
Enabled, Even Parity
Enabled, Odd Parity
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
Table 18-6.
USBS Bit Settings
USBSn
0
1
Stop Bit(s)
1-bit
2-bit
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
Table 18-7. UCSZn Bits Settings
UCSZn2
UCSZn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
UCSZn0
0
1
0
1
0
1
0
1
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 18-8. UCPOLn Bit Settings
UCPOLn
Transmitted Data Changed
(Output of TxDn Pin)
0
Rising XCKn Edge
1
Falling XCKn Edge
Received Data Sampled
(Input on RxDn Pin)
Falling XCKn Edge
Rising XCKn Edge
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